MW Enterprises
Universal Cross Assembler
Information about the Cross-32 Meta Assembler + Assembler tables for Zilog & Hitachi microcontrollers

The Cross-32 Meta Assembler is a set of table-based cross assembler software that ran under DOS and/or Windows and was originally supplied by a company in Canada called Universal Cross Assemblers. This page provides links to some tables created by MWE for the assembler and also some general information.

Content revision history:

Somewhere between 1996 and 2000 the Canadian company that developed the assembler software seemed to become unavailable and, as far as I can ascertain, has stopped supporting its creation although in September 2010, version 4.x of the software appeared to still be available for purchase from a company called Microprocessor Engineering in the UK, a company called DataSync Engineering in America.  Prior to this, in March 2002, products with different names but that were apparently the same cross-assembler were found on the internet from companies in Germany and the UK.  You could also Search AltaVista for “cross-32 meta assembler” and see if that yields anything useful. 

I still use the Version 3.0 for MS-DOS of the assembler and have found it to be reliable.  However, for my convenience I have modified some of the original definition tables and created new ones.

Target device & table

Description of table


Assembler table for Zilog Z8 microcontrollers

Zilog web site

Modified original table to add missing watchdog mnemonics and correct the opcode for one mnemonic that was wrong in the table supplied with the software.

Used extensively, no known problems

Assembler table for Hitachi H8-300


Renesas website
(Renesas have adopted the Hitachi microcontrollers)

Modified original table to correct wrong op code for the BIST instruction and to add BZ and BNZ instructions; these refer to the same op-codes as BEQ and BNE and can be used interchangeably.  Often it is convenient to think in terms of zero instead of equality and non-zero instead of inequality.

Used extensively, no known problems.

Assembler table for Hitachi H8S/2148 normal mode


Renesas website
(Renesas have adopted the Hitachi microcontrollers)

The H8S series of microcontrollers can operate in an advanced mode (24-bit addressing) and a normal mode (16-bit addressing).  The internal registers move address according to which mode is used and hence some of the instructions will access different addresses.  This means it is necessary to know which mode the microcontroller is using at assembly time in order that appropriate addresses can be generated.

The problem is particularly evident with an instruction such as BLD #3, @0xFF42 which should generate a reference to the top memory page in normal mode but should generate code to reference an absolute 16-bit address in expanded mode.  Also an instruction such as MOV @aa:16, Rn is able to access quite different memory areas in the two modes.

For this reason there are presently two versions of the table.  The table for “normal” mode (16-bit addressing) has been used for one major project and no problems were encountered although not every instruction has been implemented.  The table for “advanced” mode (24-bit addressing) is presently being used and developed.  Various problems have been encountered and although these have been resolved it would be most unwise to consider this version of the table fully reliable.

The format of the instruction mnemonics generally follows the Hitachi databook although a few “enhancements” have been included.  For example, the leading “@” is optional when used with jmp and jsr instructions except when the operand is a register.  This has been done to make the jmp and jsr instructions consistent with the branch instructions and also logically consistent with the use of the @ symbol with the “mov” instruction.

Sample Code Hitachi rules My rules
jsr @r5 Legal Legal
jsr r5 r5 will be treated as label not as a register name. Legal
jsr @SomeFunctionName Legal Legal
jsr SomeFunctionName Illegal Legal
jsr @@AbsoluteAddress Legal Not implemented

As at 29th April 2004 these tables needed to be tidied-up and they were also incomplete because certain instructions (LDM & STM, the advanced variants of LDC, jmp @@ & jsr@@, and most H8S/2600 instructions ...) had not been implemented.

The version for mode 1 (16-bit address space) was revised on 4th Jan 2003.  Used on one major project with no identified problems.

There are comments within the file; you are advised to read them before deployment.

Assembler table for Hitachi H8S/2148 advanced mode


Renesas website
(Renesas have adopted the Hitachi microcontrollers)

Revised 29th April 2004.  Under development.  Used for one project and had no known problems but this table should not be considered to be either complete or extensively tested.

These tables are archived here for my own use.  However I am quite happy for other people to use them because I have benefited greatly from other people's free software and internet pages and this is just a very minor contribution to the pool.  If you want to download them and use them for commercial or personal projects then you may do so but they may not be sold or resold or distributed for profit.  I do not guarantee that they are correct or that they will do what they are supposed to do and I do not accept any responsibility for what happens when you do you use them.  In short, use them at your own risk.

The original “C32C.EXE” assembler software is, I presume, covered by copyright and consequently I will not supply anybody with a copy of it.  However, if you are feeling lucky or desperate, you could try the following searches and see what turns up:

Search AltaVista for C32C.EXE.

Search Google for C32C.EXE


Disclaimer (the small print):  The information within this page and within this web site is offered merely in the hope that somebody somewhere might find something of it that is useful in some matter.  It is not guaranteed to be accurate or reliable in any way and you rely upon it entirely at your own risk.
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